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74AC109 数据手册 ( 数据表 ) - Motorola => Freescale

零件编号产品描述(功能)生產廠家
74AC109 Dual JK positive edge-triggered flip-flop Motorola
Motorola => Freescale Motorola
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74AC109 Datasheet PDF : 74AC109 pdf   
MC74ACT109D image

The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH

• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs

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74AC109 有关数据资料列表

零件编号产品描述(功能)PDF生產廠家
MC74AC109ML1 Dual JK Positive Edge-Triggered Flip-Flop MC74AC109ML1 View ON Semiconductor
74F109 Dual JK Positive Edge-Triggered Flip-Flop 74F109 View Fairchild Semiconductor
SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop SN74LS109A View ON Semiconductor
DV74AC109 Dual JK Positive Edge-Triggered Flip-Flop DV74AC109 View AVG Semiconductors=>HITEK
74AC109 Dual JK Positive Edge−Triggered Flip−Flop 74AC109 View ON Semiconductor
HD74AC112 Dual JK Negative Edge-Triggered Flip-Flop HD74AC112 View Hitachi -> Renesas Electronics
74AC109 Dual JK Positive Edge-Triggered Flip-Flop 74AC109 View Fairchild Semiconductor
DV74AC112 Dual JK Negative Edge-Triggered Flip-Flop DV74AC112 View AVG Semiconductors=>HITEK
74F113 Dual JK Negative Edge-Triggered Flip-Flop 74F113 View Fairchild Semiconductor
74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears 74F114 View Fairchild Semiconductor

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