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74F109 数据手册 ( 数据表 ) - Fairchild Semiconductor

零件编号产品描述(功能)生產廠家
74F109 Dual JK Positive Edge-Triggered Flip-Flop Fairchild
Fairchild Semiconductor Fairchild
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74F109 Datasheet PDF : 74F109 pdf   
74F109 image

General Description
The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs.

Asynchronous Inputs:
   LOW input to SD sets Q to HIGH level
   LOW input to CD sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CD and SD makes
      both Q and Q HIGH

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74F109 有关数据资料列表

零件编号产品描述(功能)PDF生產廠家
MC74AC109ML1 Dual JK Positive Edge-Triggered Flip-Flop MC74AC109ML1 View ON Semiconductor
SN54LS109AJ DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP SN54LS109AJ View Motorola => Freescale
SN54LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP SN54LS109A View Motorola => Freescale
SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop SN74LS109A View ON Semiconductor
DV74AC109 Dual JK Positive Edge-Triggered Flip-Flop DV74AC109 View AVG Semiconductors=>HITEK
74AC109 Dual JK positive edge-triggered flip-flop 74AC109 View Motorola => Freescale
74AC109 Dual JK Positive Edge−Triggered Flip−Flop 74AC109 View ON Semiconductor
HD74AC112 Dual JK Negative Edge-Triggered Flip-Flop HD74AC112 View Hitachi -> Renesas Electronics
DV74AC112 Dual JK Negative Edge-Triggered Flip-Flop DV74AC112 View AVG Semiconductors=>HITEK
MC74F112D DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP MC74F112D View Motorola => Freescale

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