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HD74AC112 数据手册 ( 数据表 ) - Hitachi -> Renesas Electronics

零件编号产品描述(功能)生產廠家
HD74AC112 Dual JK Negative Edge-Triggered Flip-Flop Hitachi
Hitachi -> Renesas Electronics Hitachi
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HD74AC112 Datasheet PDF : HD74AC112 pdf   
HD74LS112 image

Description
The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.

Features
• Outputs Source/Sink 24 mA
• HD74ACT112 has TTL-Compatible Inputs

 

HD74AC112 有关数据资料列表

零件编号产品描述(功能)PDF生產廠家
DV74AC112 Dual JK Negative Edge-Triggered Flip-Flop DV74AC112 View AVG Semiconductors=>HITEK
MC74F112D DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP MC74F112D View Motorola => Freescale
SN54LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP SN54LS107A View Motorola => Freescale
MC74AC113 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP MC74AC113 View Motorola => Freescale
74F113 Dual JK Negative Edge-Triggered Flip-Flop 74F113 View Fairchild Semiconductor
74F112 Dual JK Negative Edge-Triggered Flip-Flop 74F112 View Fairchild Semiconductor
74LS73 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY 74LS73 View Motorola => Freescale
74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears 74F114 View Fairchild Semiconductor
SN54LS113A Dual JK negative edge-triggered flip-flop SN54LS113A View Motorola => Freescale
MC74AC112 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP MC74AC112 View Motorola => Freescale

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