74LV374 查看數據表（PDF） - Philips Electronics

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74LV374

Octal D-type flip-flop; positive edge-trigger (3-State)

Philips Electronics 

Philips Semiconductors

Octal D-type flip-flop; positive edge-trigger (3-State)

Product specification

74LV374

AC WAVEFORMS

VM = 1.5V at VCC w 2.7V v 3.6V

VM = 0.5V * VCC at VCC t 2.7V and w 4.5V

VOL and VOH are the typical output voltage drop that occur with the

output load.

CP INPUT

Qn OUTPUT

1/fmax

VM

tW

tPHL

90%

tTHL

VM

10%

tPLH

tTLH

SV00343

Figure 1. Waveforms showing the clock (CP) to output (Qn)

propagation delays, the clock pulse width, output transition

times and the maximum clock pulse frequency

VI

OE INPUT

GND

VCC

OUTPUT

LOW-to-OFF

OFF-to-LOW

VOL

VM

tPLZ

VX

tPHZ

tPZL

VM

tPZH

VOH

OUTPUT

HIGH-to-OFF

OFF-to-HIGH

GND

VY

outputs

enabled

outputs

disabled

VM

outputs

enabled

SV00344

Figure 2. Waveforms showing the 3-state enable and disable

times

VI

CP INPUT

VM(1)

GND

tsu

tsu

VI

ÌÌÌÌ Dn INPUT

VM

ÌÌÌÌÌÌÌÌ GND

ÌÌÌth ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌthÌÌÌ

VOH

Qn OUTPUT

VM

VOL

NOTE: the shaded areas indicate when the input is permitted to change

for predictable output performance.

SV00345

Figure 3. Waveforms showing the data set-up and hold times

for the Dn input to the CP input

NOTE:

The shaded areas indicate when the input is permitted to change for

predictable output performance.

1997 Mar 20

7

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