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TLP651 查看數據表(PDF) - Toshiba

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TLP651 Datasheet PDF : 7 Pages
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TLP651
(Note 8) CML is the maximum rate of fall of the common mode voltage that can be sustained with the output
voltage in the logic low state (VO < 0.8V).
CMH is the maximum rate of rise of the common mode voltage that can be sustained with the output
voltage in the logic high state (VO > 2.0V).
(Note 9) Maximum electrostatic discharge voltage for any pins: 100V (C = 200pF, R = 0).
Test Circuit 1: Switching Time Test Circuit
Test Circuit 2: Common Mode Noise Immunity Test Circuit
4
2007-10-01

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