IMIC9531CT(2003) 查看數據表（PDF） - Cypress Semiconductor
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IMIC9531CT Datasheet PDF : 10 Pages
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Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Description
20:27
28
29:36
37
38:45
46
....
....
....
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
Data Byte (N–1) – 8 bits
Acknowledge from slave
....
Data Byte N – 8 bits
....
Acknowledge from slave
....
Stop
C9531
Table 3. SMBus Address Selection Table
SMBus Address of the Device
DE
DC
DA
D8
D6
D4
D0
D2
IA0 Bit (Pin 10)
0
1
0
1
0
1
0
1
IA1 Bit (Pin 11)
0
0
1
1
0
0
1
1
IA2 Bit (Pin 12)
0
0
0
0
1
1
1
1
Serial Control Registers
Byte 0: Output Register
Bit
@Pup
7
1
6
0
5
1
4
0
3
0
Name
TESTEN
SSEN
SSSEL
S1
S0
Description
Test Mode Enable.
1 = Normal operation, 0 = Test mode
Spread Spectrum modulation control bit (effective only when Bit 0 of this register is
set to a 0) 0 = OFF, 1= ON
SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table 4 below for clarification
S1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
S0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
Document #: 38-07034 Rev. *D
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