Timing Chart
1/Fsftclk
Dsftclk/Fsftclk
SFTCLK
2.0V
0.8V
Tir
Tif
Setup/hold time is refered from
fall edge in TESTSB/DT = GND or OPEN
rise edge in TESTSB/DT=V CC
Tir
REDxx
GRNxx
BLUxx
H/Vsync
CNTLx
Tsetup
2.0V
0.8V
Tif
Fig. 4. TTL input timing
SDATAP
SDATAN
Tor
80%
20%
Tof
Fig. 5. Serial output timing
SDATAP
SDATAN
REFRQ
signal from
CXB1452Q
REFREQ
Reference clock
NRZ data
TDclk
Fig. 6. Refclk request timing
CXB1451Q
VIH_T
Vth
VIL_T
Thold
VIH_T
VIL_T
100%
0%
TAclk
IDLE
SDATAP
SDATAN
NRZ data
TDidle
Fig. 7. Idle mode timing
–6–
TAidle