IDT72510L25J 查看數據表（PDF） - Integrated Device Technology

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IDT72510L25J

BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT – 1024 x 9-BIT 1024 x 18-BIT – 2048 x 9-BIT

Integrated Device Technology 

IDT72510, IDT72520

BUS MATCHING BIDIRECTIONAL FIFO

36-BIT PROCESSOR to 9-BIT PERIPHERAL CONFIGURATION

COMMERCIAL TEMPERATURE RANGE

Processor

Address

Control

Data

RAM

IDT

BiFIFO

(Master)

Cntl A Cntl B

ACK

REQ

CLK

Data A Data B

IDT

BiFIFO

(Slave)

Cntl A Cntl B

ACK

REQ

CLK

Data A Data B

18

DMA or

System

Clock

Peripheral

Controller

Cntl

ACK

REQ

Data

I/O

Data

2669 drw 07

Figure 4. 36- to 9-Bit Peripheral Interface Configuration

NOTE:

1. Cntl A refers to CSA, A1, A0, R/WA and DSA; Cntl B refers to R/WB and DSB or RB and WB.

5.31

9

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