MC54HCT163A 查看數據表（PDF） - Motorola => Freescale

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MC54HCT163A

Presettable Counters

Motorola => Freescale 

MC54/74HCT161A MC54/74HCT163A

3

P0

4

P1

5

P2

6

P3

7

Enable P

10

Enable T

1

Reset

9

Load

2

Clock

T0

R

Q0

C

C

Load

Load Q0

P0

T1

R

Q1

C

C

Load

Load Q1

P1

T2

R

Q2

C

C

Load

Load Q2

P2

T3

R

Q3

C

C

Load

Load

P3

14

Q0

13

Q1

12

Q2

11

Q3

15 Ripple

Carry Out

The flip–flops shown in the circuit diagrams are Toggle–

R

Enable flip–flops. A Toggle–Enable flip–flop is a combina-

tion of a D flip–flop and a T flip–flop. When loading data

Load

Load

from Preset inputs P0, P1, P2 and P3, the Load signal is

used to disable the Toggle input (Tn) of the flip–flop. The

logic level at the Pn input is then clocked to the Q output of

C

the flip–flop on the next rising edge of the clock.

A logic zero on the Reset device input forces the internal

C

clock (C) high and resets the Q output of the flip–flop low.

Figure 8. 4–Bit Binary Counter with Asynchronous Reset (MC54/74HCT161A)

MOTOROLA

6

High–Speed CMOS Logic Data

DL129 — Rev 6

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