U634H256 查看數據表（PDF） - Zentrum Mikroelektronik Dresden AG
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U634H256 Datasheet PDF : 14 Pages
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Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
U634H256
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previous Data Valid
tv(A) (9)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
High Impedance
ACTIVE
ten(G) (8)
tPU (10)
STANDBY
tPD (11)
tdis(E) (5)
tdis(G) (6)
Output Data Valid
No.
Switching Characteristics
Write Cycle
Symbol
25
35
45
Unit
Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
tAVAV
tAVAV
tcW
25
35
45
ns
13 Write Pulse Width
tWLWH
tw(W)
20
25
30
ns
14 Write Pulse Width Setup Time
tWLEH
tsu(W)
20
25
30
ns
15 Address Setup Time
tAVWL
tAVEL
tsu(A)
0
0
0
ns
16 Address Valid to End of Write
tAVWH
tAVEH tsu(A-WH) 20
25
30
ns
17 Chip Enable Setup Time
tELWH
tsu(E)
20
25
30
ns
18 Chip Enable to End of Write
tELEH
tw(E)
20
25
30
ns
19 Data Setup Time to End of Write tDVWH tDVEH tsu(D) 10
12
15
ns
20 Data Hold Time after End of Write tWHDX tEHDX
th(D)
0
0
0
ns
21 Address Hold after End of Write
tWHAX
tEHAX
th(A)
0
0
0
ns
22 W LOW to Output in High-Zh, i
tWLQZ
tdis(W)
10
13
15 ns
23 W HIGH to Output in Low-Z
tWHQX
ten(W)
5
5
5
ns
April 21, 2004
5
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