A43L0632G-7F 查看數據表（PDF） - AMIC Technology

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A43L0632G-7F

512K X 32 Bit X 2 Banks Synchronous DRAM

AMIC Technology 

A43L0632

12. About Burst Type Control

Basic

MODE

Random

MODE

Sequential counting

Interleave counting

Random column Access

tCCD = 1 CLK

At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)

BL=1,2,4,8 and full page wrap around.

At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)

BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting

Every cycle Read/Write Command with random column address can realize

Random Column Access.

That is similar to Extended Data Out (EDO) Operation of convention DRAM.

13. About Burst Length Control

Basic

MODE

Special

MODE

Interrupt

MODE

1

At MRS A2,1,0 = “000”.

At auto precharge, tRAS should not be violated.

2

At MRS A2,1,0 = “001”.

At auto precharge, tRAS should not be violated.

4

At MRS A2,1,0 = “010”

8

At MRS A2,1,0 = “011”.

At MRS A9=”1”.

BRSW

Read burst = 1,2,4,8, full page/write Burst =1

At auto precharge of write, tRAS should not be violated.

Before the end of burst, Row precharge command of the same bank

RAS Interrupt

Stops read/write burst with Row precharge.

(Interrupted by Precharge) tRDL= 2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively

During read/write burst with auto precharge, RAS interrupt cannot be issued.

Before the end of burst, new read/write stops read/write burst and starts new

CAS Interrupt

read/write burst or block write.

During read/write burst with auto precharge, CAS interrupt can not be issued.

PRELIMINARY (February, 2007, Version 0.1)

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AMIC Technology, Corp.

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