PDM31564SA 查看數據表（PDF） - Paradigm Technology

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PDM31564SA

256K x 16 CMOS 3.3V Static RAM

Paradigm Technology 

PRELIMINARY

PDM31564

Write Cycle 1 Timing Diagram (WE Controlled)

tWC

ADDRESSES

tAW

tAS

tWP

tAH

WE

tCW

CE

tBW

UB, LB

DOUT

tHZWE(1)

(3)

High Impedance

tDS

tLZWE(1)

(4)

tDH

DIN

Data Stable

Write Cycle 2 Timing Diagram (CE Controlled)

tWC

ADDRESSES

tAS

tAW

tWP

WE

tCW

CE

tBW

UB, LB

DOUT

tLZBE(1)

tLZCE(1)

tHZWE(1)

tAH

High Impedance

tDS

tDH

DIN

Data Stable

1

2

3

4

5

6

7

8

9

10

11

12

Rev. 1.2 - 3/31/98

7

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