CLK1,
CLK0
ADS0
A(12, 13,
14 – 26)
CWE0 –
CWE7
STANDBY
CNTEN0
SYNCHRONOUS DATA RAM WRITE CYCLE
tKHKH
tKLKH
tKHKL
tSVKH
tKHTSX
tAVKH
tKHAX tAVKH
A1
tKHAX
A2
tWVKH
tKHWX
tEVKH
tKHEX
tBAVKH
tKHBAX
DATA IN
D (A1)
tDVKH
D (A2)
tKHDX
D (A2 + 1)
D (A2 + 2)
D (A2 + 3)
SINGLE WRITE
BURST WRITE
NOTES:
1. Cache addresses used are: 14 – 26 for MPC2104 and MPC2107; 13 – 26 for MPC2105; and 12 – 26 for MPC2106.
2. COE0 = VIH
MOTOROLA FAST SRAM
MPC2104•MPC2105•MPC2106•MPC2107
11