DS2165 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS2165

16/24/32kbps ADPCM Processor

Dallas Semiconductor -> Maxim Integrated 

Figure 1. BLOCK DIAGRAM

DS2165Q

Figure 2. SERIAL PORT WRITE

Note: A 2-byte write is shown.

The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or

compression occurs. Bypass operates on bytewide (8 bits) slots when CP/ EX is set and on nibble-wide

(4 bits) slots when CP/ EX is cleared.

A-law (U/ A = 0) and m-law (U/ A = 1) PCM coding is independently selected for the X and Y channels

by CR.2. If BYP and IPD are cleared, then CP/ EX determines if the input data is to be compressed or

expanded.

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