GS71116AJ 查看數據表（PDF） - Unspecified

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GS71116AJ

64K x 16 1Mb Asynchronous SRAM

Unspecified 

Write Cycle 3: UB, LB control

Address

OE

CE

UB, LB

WE

Data In

Data Out

GS71116ATP/J/U

tWC

tAW

tWR1

tAS

tCW

tBW

tWP

tDW tDH

Data valid

High impedance

Rev: 1.04a 10/2002

10/15

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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