IDT71256 查看數據表（PDF） - Integrated Device Technology
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IDT71256
Integrated Device Technology
IDT71256 Datasheet PDF : 9 Pages
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IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
OE
CS
DATA OUT
tAA
tOE
tOLZ (5)
tACS
tCLZ (5)
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
ADDRESS
DATA OUT
tRC
tAA
tOH
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS
DATA OUT
tACS
tCLZ (5)
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tOH
tOHZ (5)
tCHZ (5)
2946 drw 07
tOH
2946 drw 08
tCHZ (5)
2946 drw 09
7.2
7
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