KA7500CDTF 查看數據表（PDF） - Fairchild Semiconductor

零件编号

产品描述 (功能)

比赛名单

KA7500CDTF

SMPS Controller

Fairchild Semiconductor 

Physical Dimensions

10.10

9.70

A

9.08

8.68

0.65

16

9

B

6.00

B

#1

(0.30)

1.80 MAX

1.65

1.45

1.27

TOP VIEW

4.15

3.75

5.60

B

8

0.51

0.36

0.20

CBA

1.75

#1

1.27

LAND PATTERN RECOMMENDATION

SIDE VIEW

(R0.20)

c

0.05 MIN

0.10 MAX C

SEE DETAIL A

0.303

0.153

B

END VIEW

NOTES:

A) THIS DRAWING GOMPLIES WITH JEDEC MS-012

EXCEPT AS NOTED.

B) THIS DEMENSION IS OUTSIDE THE JEDEC MS-012 VALUE.

C) ALL DIMENSIONS ARE IN MILLIMETERS.

D) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS.

E) LANDPATTERN STANDARD: SOIC127P600X175-16AM.

F) DRAWING FILE NAME AND REVISION : M16EREV1

GAGE

PLANE

0.36

SEATING

PLANE

DETAIL A

Figure 3. 16-Lead Small Outline Package (SOP)

8¡Æ

(R0.10)

0.90

0.50

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

© 2003 Fairchild Semiconductor Corporation

KA7500C • Rev. 1.0.2

6

www.fairchildsemi.com

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