MB86612 查看數據表（PDF） - Fujitsu

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MB86612

IEEE 1394 Bus Controller

Fujitsu 

MB86612

(Continued)

• Built-in CSR's to provide isochronous resource manager functions

• 32-bit CRC generation and check functions

• General purpose port for asynchronous transfer and control (16-bit MPU bus)

• Exclusive built-in ports for isochronous transfer (8-bit bus)

• Built-in CRS's and automatic processes to support AV/C protocol (MPEG, DVC)

1) Automatic separation of CIP headers at receiving, and automatic packetizing at sending.

2) Automatic generation of source packet headers (time stamp).

3) Source packet header (time stamp) match detection

4) DBC area automatic increment function

5) Empty packet sending and receiving

6) On-chip PCR (input/output 1 channel each)

7) Each CSR with automatic C&S lock processing and read processing

8) Automatic processing of late packet generation

• Compatible with 4-core or 6-core cables

• Packages: LQFP-100, FBGA-120

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