SL74HC597N 查看數據表（PDF） - System Logic Semiconductor
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SL74HC597N
System Logic Semiconductor
SL74HC597N Datasheet PDF : 9 Pages
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SL74HC597
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax Minimum Clock Frequency (50% Duty Cycle)
(Figures 2 and 8)
tPLH, tPHL Maximum Propagation Delay, Latch Clock to QH
(Figures 1 and 8)
tPLH, tPHL Maximum Propagation Delay , Shift Clock to QH
(Figures 2 and 8)
tPHL Maximum Propagation Delay , Reset to QH
(Figures 3 and 8)
tPLH, tPHL Maximum Propagation Delay, Serial Shift/
Parallel Load to QH (Figures 4 and 8)
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 8)
CIN
Maximum Input Capacitance
VCC
Guaranteed Limit
V 25 °C to ≤85°C ≤125°C Unit
-55°C
2.0 6.0
4.8
4.0 MHz
4.5 30
24
20
6.0 35
28
24
2.0 210
265
315
ns
4.5 42
53
63
6.0 36
45
54
2.0 175
220
265
ns
4.5 35
44
53
6.0 30
37
45
2.0 175
220
265
ns
4.5 35
44
53
6.0 30
37
45
2.0 175
220
265
ns
4.5 35
44
53
6.0 30
37
45
2.0 75
95
110
ns
4.5 15
19
22
6.0 13
16
19
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
50
pF
SLS
System Logic
Semiconductor
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