CY7C025AV-20AI 查看數據表（PDF） - Cypress Semiconductor

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CY7C025AV-20AI

3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

Cypress Semiconductor 

PRELIMINARY

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

Switching Waveforms (continued)

Semaphore Read After Write Timing, Either Side[37]

A 0–A 2

SEM

VALID ADRESS

tAW

tHA

tSCE

tSAA

VALID ADRESS

tSOP

tACE

tOHA

I/O 0

R/W

OE

tSD

DATAIN VALID

tSA

tPWE

tHD

DATAOUT VALID

WRITE CYCLE

tSWRD

tSOP

tDOE

READ CYCLE

Timing Diagram of Semaphore Contention[38, 39, 40]

A0L –A2L

MATCH

R/WL

SEM L

A 0R–A2R

R/WR

SEM R

tSPS

MATCH

Notes:

37. CE = HIGH for the duration of the above timing (both write and read cycle).

38. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.

39. Semaphores are reset (available to both ports) at cycle start.

40. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.

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