UPD72873 查看數據表（PDF） - NEC => Renesas Technology

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UPD72873

IEEE1394 OHCI 1.1 COMPLIANT 2PORT PHY-LINK 1-CHIP HOST CONTROLLER

NEC => Renesas Technology 

µPD72873

Name

I/O

Pin No.

IOL

Volts(V)

Function

CLKRUN

I/O 2

PCI/Cardbus 5/3.3 PCICLK Running as input, to determine the status

of PCLK; as output, to request starting or speeding

up clock.

INTA

O4

PCI/Cardbus 5/3.3 Interrupt the PCI interrupt request A.

PERR

I/O 41

PCI/Cardbus

5/3.3

Parity Error is used for reporting data parity errors

during all PCI transactions, except a special cycle.

It is an output when AD0 to AD31 and PAR are both

inputs. It is an input when AD0 to AD31 and PAR

are both outputs.

SERR

O 42

PCI/Cardbus 5/3.3 System Error is used for reporting address parity

errors, data parity errors during the special cycle, or

any other system error where the effect can be

catastrophic. When reporting address parity errors,

it is an output.

PRST

I5

-

5/3.3 Reset PCI reset

PCLK

I6

-

5/3.3 PCI Clock 33 MHz system bus clock.

Remark *: If the Link pin is pulled up, it should be connected to L_VDD.

(2/2)

Block *

Link

Link

Link

Link

Link

Link

Preliminary Data Sheet S15305EJ2V0DS

9

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