ZR36067 查看數據表（PDF） - Unspecified
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ZR36067 Datasheet PDF : 48 Pages
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15.0 AC TIMING SPECIFICATIONS
15.1 PCI Bus Timing
Table 18: PCI Bus Timing
Symbol
tPCI
tPH
tPL
tA3
tA4
tA5
tA6
tA7
tA8
tA9
tA10
tA11
Parameter
PCICLK period
PCICLK high
PCICLK low
PCICLK slew rate
PCICLK to signal valid delay - bussed signals
PCICLK to signal valid delay - point-to-point
Float to active delay
Active to float delay
Input setup time to PCICLK - bussed signals
Input setup time to PCICLK - point-to-point
Input hold time from PCICLK
Unloaded output rise/fall time
AV PCI CONTROLLER
Min
Max
Unit
30
ns
12
ns
12
ns
1
4
V/ns
2
11
ns
2
12
ns
2
11
ns
28
ns
7
ns
10
ns
0
ns
1
5
V/ns Between 0.4 V and 2.4 V
PCICLK
Output Delay
tPCI
tPH
tPL
tA4
tA5
tA6
tA7
3-State Output
tA8
tA9
tA10
Input
tA3
tA11
Figure 10. PCI Bus Timing
37
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