HEC4007UBDB 查看數據表（PDF） - Philips Electronics

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HEC4007UBDB

Dual complementary pair and inverter

Philips Electronics 

Philips Semiconductors

Dual complementary pair and inverter

Product specification

HEF4007UB

gates

Fig.14 High impedance buffer.

FUNCTION TABLE for Fig.14.

INPUT

H

L

X

DISABLE

L

L

H

OUTPUT

L

H

open

Notes

1. H = HIGH state (the more positive voltage)

L = LOW state (the less positive voltage)

X = state is immaterial

NOTE

Rules for maintaining electrical isolation between

transistors and monolithic substrate:

• Pin number 14 must be maintained at the most positive

(or equally positive) potential with respect to any other

pin of the HEF4007UB.

• Pin number 7 must be maintained at the most negative

(or equally negative) potential with respect to any other

pin of the HEF4007UB.

Violation of these rules will result in improper transistor

operation and/or possible permanent damage to the

HEF4007UB.

January 1995

8

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