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零件编号
产品描述 (功能)
CXB1582Q 查看數據表(PDF) - Sony Semiconductor
零件编号
产品描述 (功能)
比赛名单
CXB1582Q
Fibre Channel Receiver
Sony Semiconductor
CXB1582Q Datasheet PDF : 23 Pages
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CXB1582Q
Pin
No.
Symbol
Type
Typical pin
I/O voltage
36 LKDT
∗
TTL
output
TTL level
Equivalent circuit
V
CC
T5
V
CC
T3
LKDT
∗
V
CC
G
V
EE
T
Description
PLL lock detection
signal output.
This pin outputs low
level when the PLL is
locked to the serial
data and high level
when the PLL
becomes unlocked.
37 SSEL1
38 SSEL0
TTL
input
TTL level
SSEL0
SSEL1
SOUT/SOUT
∗
output
signal selection.
(See Table 1.)
V
EE
T
V
EE
T
V
CC
G
39 PDTEST
TTL
input
0V
PDTEST
Test.
Connect to V
EE
G.
V
EE
T
V
CC
G
40
ECLKSEL
∗
TTL
input
TTL high
level or 3.3V
ECLKSEL
∗
V
EE
T
–6–
V
EE
T
External clock
selection.
When this pin is set
to low level, the clock
input to EXCLK is
used as the bit rate
clock.
V
EE
T
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