MC74HC390 查看數據表（PDF） - ON Semiconductor

零件编号

产品描述 (功能)

比赛名单

MC74HC390

Dual 4-Stage Binary Ripple Counter with ÷2 and ÷5 Sections

ON Semiconductor 

MC54/74HC390

PIN DESCRIPTIONS

INPUTS

Clock A (Pins 1, 15) and Clock B (Pins 4, 15)

Clock A is the clock input to the ÷ 2 counter; Clock B is the

clock input to the ÷ 5 counter. The internal flip–flops are

toggled by high–to–low transitions of the clock input.

CONTROL INPUTS

Reset (Pins 2, 14)

Asynchronous reset. A high at the Reset input prevents

counting, resets the internal flip–flops, and forces QA through

QD low.

OUTPUTS

QA (Pins 3, 13)

Output of the ÷ 2 counter.

QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)

Outputs of the ÷ 5 counter. QD is the most significant bit.

QA is the least significant bit when the counter is connected

for BCD output as in Figure 4. QB is the least significant bit

when the counter is operating in the bi–quinary mode as in

Figure 5.

SWITCHING WAVEFORMS

tf

tr

90%

VCC

tw

CLOCK

50%

VCC

10% 10%

GND

RESET

50%

tw

1/fmax

GND

tPHL

tPLH

90%

Q

50%

10%

tTLH

tPHL

tTHL

Q

CLOCK

50%

trec

VCC

50%

GND

Figure 1.

Figure 2.

TEST CIRCUIT

TEST POINT

OUTPUT

DEVICE

UNDER

TEST

CL*

* Includes all probe and jig capacitance

Figure 3.

MOTOROLA

4

High–Speed CMOS Logic Data

DL129 — Rev 6

Share Link: