SL74HCT573 查看數據表（PDF） - System Logic Semiconductor
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SL74HCT573 Datasheet PDF : 6 Pages
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SL74HCT573
AC ELECTRICAL CHARACTERISTICS(VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25 °C to ≤85°C ≤125°C Unit
-55°C
tPLH, tPHL MaximumPropagation Delay, Input D to Q
(Figures 1 and 5)
30
38
45
ns
tPLH, tPHL Maximum Propagation Delay,Latch Enable
to Q (Figures 2 and 5)
30
38
45
ns
tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q
28
35
(Figures 3 and 6)
42
ns
tPZH, tPZL Maximu m Propagation Delay, Output Enable to Q
28
35
(Figures 3 and 6)
42
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 5)
12
15
18
ns
CIN
Maximum Input Capacitance
COUT Maximum Three-State Output Capacitance
(Output in High-Impedance State)
10
10
15
15
10
pF
15
pF
Power Dissipation Capacitance (Per Enabled
Output)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
48
pF
TIMING REQUIREMENTS (VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25 °C to
-55°C
≤85°C
≤125°C
Unit
tSU
Minimum Setup Time, Input D
10
13
15
ns
to Latch Enable
(Figure 4)
th
Minimum Hold Time, Latch
5
5
5
ns
Enable to Input D
(Figure 4)
tw
Minimum Pulse Width, Latch
15
19
22
ns
Enable (Figure 2)
tr, tf Maximum Input Rise and Fall
500
500
500
ns
Times (Figure 1)
SLS
System Logic
Semiconductor
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