LC4064ZE 查看數據表（PDF） - Lattice Semiconductor

零件编号

产品描述 (功能)

生产厂家

LC4064ZE

1.8V In-System Programmable Ultra Low Power PLDs

Lattice Semiconductor 

Lattice Semiconductor

Figure 9. Power Guard

ispMACH 4000ZE Family Data Sheet

Power Guard

0

D

Q

1

E

All the I/O pins in a block share a common Power Guard Enable signal. For a block of I/Os, this signal is called a

Block Input Enable (BIE) signal. BIE can be internally generated using MC logic, or could come from external

sources using one of the user I/O or input pins.

Any I/O pin in the block can be programmed to ignore the BIE signal. Thus, the feature can be enabled or disabled

on a pin-by-pin basis.

Figure 10 shows Power Guard and BIE across multiple I/Os in a block that has eight I/Os.

Figure 10. Power Guard and BIE in a Block with 8 I/Os

Power Guard

0

To Macrocell

1

I/O 0

To GRP

Block Input Enable (BIE)

From Block PT. The Block PT

is part of the block AND Array,

and can be driven by signals

from the GRP.

To Macrocell

To GRP

Power Guard

0

1

I/O 1

To Macrocell

To GRP

Power Guard

0

1

I/O 7

11

Share Link: