HM5264165F-75 查看數據表（PDF） - Elpida Memory, Inc

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比赛名单

HM5264165F-75

64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5264165F/HM5264805F/HM5264405F-75/A60/B60

• Programmable CAS latency: 2/3

• Byte control by DQM: DQM (HM5264805F/HM5264405F)

DQMU/DQML (HM5264165F)

• Refresh cycles: 4096 refresh cycles/64 ms

• 2 variations of refresh

 Auto refresh

 Self refresh

• Full page burst length capability

 Sequential burst

 Burst stop capability

Ordering Information

Type No.

Frequency

CAS latency

HM5264165FTT-75*1

133 MHz

3

HM5264165FTT-A60

100 MHz

2/3

HM5264165FTT-B60*2

100 MHz

3

HM5264165FLTT-75*1

133 MHz

3

HM5264165FLTT-A60

100 MHz

2/3

HM5264165FLTT-B60*2 100 MHz

3

HM5264805FTT-75*1

133 MHz

3

HM5264805FTT-A60

100 MHz

2/3

HM5264805FTT-B60*2

100 MHz

3

HM5264805FLTT-75*1

133 MHz

3

HM5264805FLTT-A60

100 MHz

2/3

HM5264805FLTT-B60*2 100 MHz

3

HM5264405FTT-75*1

133 MHz

3

HM5264405FTT-A60

100 MHz

2/3

HM5264405FTT-B60*2

100 MHz

3

HM5264405FLTT-75*1

133 MHz

3

HM5264405FLTT-A60

100 MHz

2/3

HM5264405FLTT-B60*2 100 MHz

3

Note: 1. 100 MHz operation at CAS latency = 2.

2. 66 MHz operation at CAS latency = 2.

Package

400-mil 54-pin plastic TSOP II (TTP-54D)

Data Sheet E0135H10

2

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