DRAIN SUPPLY
Vd = +4V
L = BOND WIRE INDUCTANCE
10,000pF
100pF L
L
100pF
L
L
L
MMIC CHIP
L
10,000pF
L
100pF
100pF
L
L
REFERENCE DETECTOR
BIAS VOLTAGE
Vrefbias (typ. -2.5V)
R = 50 kΩ
REFERENCE DETECTOR
VOLTAGE Vref
RF IN
RF OUT
GROUND
(Back of Chip)
L
100pF
L
DETECTOR
VOLTAGE Vdet
R = 50 kΩ
DETECTOR BIAS
VOLTAGE VdetBias
(typ. -2.5V)
GATE SUPPLY
Vg
Note:
For output power level detection, bias both detector and reference diodes. DC voltage difference between detector and reference can be used to
measure output power after calibration. If output power level detection is not desired, do not make connection to detector bond pad.
Figure 3. Recommended Application Schematic Circuit Diagram
DIE-ATTACH
80Au/20Sn
10, 00 0pF
Vdd (POSITIVE)
10, 00 0pF
10 0pF
5 MIL THICK
ALUMINA
50Ω
RF INPUT
10 0pF
10 0pF
10 0pF
REFERENCE DETECTOR
BIAS VOLTAGE VrefBias
50 KΩ
REFERENCE DETECTOR
VOLTAGE Vref
5 MIL THICK
ALUMINA
50
RF OUTPUT
Vg (NEGATIVE)
2 MIL GAP
DETECTOR
VOLTAGE Vdet
50 KΩ
DETECTOR
BIAS VOLTAGE Vdetbias
L < 0.015"
(2 Places)
Note:
1. Use 0.003" by 0.0005" Gold Ribbon for bonding. RF input and output bonds should be less than 0.015" long with stress relief.
2. If output power level detection is not desired, do not make connection to detector bond pad.
Figure 4. Recommended Assembly Diagram
©2004 Fairchild Semiconductor Corporation
RMWP38001 Rev. C