LC82220 查看數據表（PDF） - SANYO -> Panasonic

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产品描述 (功能)

比赛名单

LC82220

Motion JPEG Decoder LSI

SANYO -> Panasonic 

LC82220

Pin Functions

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

Symbol

I/O

VDD

ZCTLINT

O

ZCTLCS

I

ZCTLRD

I

ZCTLWR

I

ZCTLRDY

O

TEST3

I

TEST4

I

CTLA5

I

CTLA4

I

CTLA3

I

CTLA2

I

CTLA1

I

CTLA0

I

CTLCPU

I

VDD

VSS

CTLD7

I/O

CTLD6

I/O

CTLD5

I/O

CTLD4

I/O

CTLD3

I/O

CTLD2

I/O

CTLD1

I/O

CTLD0

I/O

TEST0

I

ZRESET

I

CLKSEL0

I

CLKSEL1

I

CLK

I

TEST1

I

VDD

VSS

ZCDCS/ZCDACK I

ZCDINT/ZCDREQ O

ZCDWR

I

ZCDRDY

O

CCD15

I

CCD14

I

CCD13

I

CCD12

I

CCD11

I

CCD10

I

CCD9

I

CCD8

I

CCD7

I

CCD6

I

VSS

VDD

CCD5

I

CCD4

I

CCD3

I

CCD2

I

CCD1

I

CCD0

I

+5 V power supply

Control bus interrupt request (open drain output)

Control bus select

Control bus read or R/W select

Control bus write or Data strobe

Control bus ready (tristate output)

Test pin

Test pin

Function

Control bus address

Control bus CPU type selection

+5 V power supply

Ground

Control bus data

Test pin

Hardware reset

Clock divisor setting

CLKSEL1:0 = 00: no divisor, 01: clock divided by 2, 10: clock divided by 3

System (decode) clock input (CMOS level input)

Test pin

+5 V power supply

Ground

Code bus select or Code bus DMA acknowledge

Code bus interrupt or Code bus DMA request

Code bus data write signal

Code bus ready (tristate output)

Code bus data

Ground

+5 V power supply

Code bus data

Continued on next page.

No. 5422-3/6

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