MC74HC374AFL1 查看數據表（PDF） - ON Semiconductor
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MC74HC374AFL1 Datasheet PDF : 8 Pages
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MC74HC374A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
v v 85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VOL
Maximum Low–Level Output
Voltage
v Vin = VIH or VIL
|Iout| 20 µA
2.0
0.10
0.10
0.10
V
4.5
0.10
0.10
0.10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 6.0
0.10
0.10
0.10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v Vin=VIHorVIL |Iout|
v |Iout|
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v |Iout|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Iin
Maximum Input Leakage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ IOZ
Maximum Three–State
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Leakage Current
Output in High–Impedance State
6.0
± 0.5
± 5.0
± 10
µA
Vin = VIL or VIH
Vout = VCC or GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ICC
Maximum Quiescent Supply Vin = VCC or GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Current (per Package)
Iout = 0 µA
6.0
4
40
160
µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
VCC
V
– 55 to
25_C
v v 85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ fmax
Maximum Clock Frequency (50% Duty Cycle)
2.0
6
5
4
MHz
3.0
15
10
8
4.5
30
24
20
6.0
35
28
24
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL
Maximum Propagation Delay, Input Clock to Q
(Figures 1 and 5)
2.0
125
155
190
ns
3.0
80
110
130
4.5
25
31
38
6.0
21
26
32
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
150
190
225
ns
3.0
100
125
150
4.5
30
38
45
6.0
26
33
38
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
150
190
225
ns
3.0
100
125
150
4.5
30
38
45
6.0
26
33
38
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
75
3.0
27
4.5
15
6.0
13
95
110
ns
32
36
19
22
16
19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Cin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Cout
Maximum Input Capacitance
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
10
10
10
pF
15
15
15
pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
34
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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