74LV377D 查看數據表（PDF） - Philips Electronics
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74LV377D Datasheet PDF : 12 Pages
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Philips Semiconductors
Octal D-type flip-flop with data enable;
positive edge-trigger
Product specification
74LV377
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V
VM = 0.5V * VCC at VCC t 2.7V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VCC
CP INPUT
GND
1/fmax
VM
tW
VOH
tPHL
tPLH
Qn OUTPUT
VM
VOL
SV00707
Figure 1. Clock (CP) to output (Qn) propagation delays,
the clock pulse width and the maximum clock pulse frequency.
EINPVGUCNCTDÉÉÉÉÉÉÉÉÉVM ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
VCC
ÉÉÉÉÉÉÉÉÉÉÉÉÉ Dn INPUT
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ GND
th
tsu
STABLE
VM
tsu
th
tsu
th
tW
VCC
CP INPUT
VM
GND
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SV00671
Figure 2. Data set-up and hold times from the data input (Dn)
and from the enable input (E) to the clock (CP).
TEST CIRCUIT
VCC
PULSE
GENERATOR
VI
RT
D.U.T.
VO
50pF
CL
RL = 1k
Test Circuit for switching times
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of pulse generators.
TEST
tPLH/tPHL
VCC
< 2.7V
2.7–3.6V
VI
VCC
2.7V
SV00901
Figure 3. Load circuitry for switching times
1998 Jun 10
7
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