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MC74HC240A Datasheet PDF : 8 Pages
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MC74HC240A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
High–Performance Silicon–Gate CMOS
The MC74HC240A is identical in pinout to the LS240. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed
to be used with 3–state memory address drivers, clock drivers, and
other sub–oriented systems. The device has inverting outputs and two
active–low output enables.
The HC240A is similar in function to the HC244A.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 120 FETs or 30 Equivalent Gates
LOGIC DIAGRAM
A1 2
18 YA1
A2 4
16 YA2
A3 6
14 YA3
DATA
INPUTS
A4 8
B1 11
12 YA4
9 YB1
INVERTING
OUTPUTS
B2 13
7 YB2
B3 15
5 YB3
B4 17
3 YB4
OUTPUT
ENABLES
ENABLE A 1
ENABLE B 19
FUNCTION TABLE
Inputs
Outputs
Enable A,
Enable B A, B YA, YB
L
L
H
L
H
L
H
X
Z
Z = high impedance
PIN 20 = VCC
PIN 10 = GND
http://onsemi.com
20
1
20
1
PDIP–20
N SUFFIX
CASE 738
SOIC WIDE–20
DW SUFFIX
CASE 751D
MARKING
DIAGRAMS
20
MC74HC240AN
AWLYYWW
1
20
HC240A
AWLYYWW
1 20
20
1
TSSOP–20
DT SUFFIX
CASE 948E
HC
240A
ALYW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN ASSIGNMENT
ENABLE A 1
A1 2
YB4 3
A2 4
YB3 5
A3 6
YB2 7
A4 8
YB1 9
GND 10
20 VCC
19 ENABLE B
18 YA1
17 B4
16 YA2
15 B3
14 YA3
13 B2
12 YA4
11 B1
ORDERING INFORMATION
Device
Package Shipping
MC74HC240AN
PDIP–20 1440 / Box
MC74HC240ADW
SOIC–WIDE 38 / Rail
MC74HC240ADWR2 SOIC–WIDE 1000 / Reel
MC74HC240ADT
TSSOP–20 75 / Rail
MC74HC240ADTR2 TSSOP–20 2500 / Reel
© Semiconductor Components Industries, LLC, 2000
1
May, 2000 – Rev. 9
Publication Order Number:
MC74HC240A/D
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