LC89975M 查看數據表（PDF） - SANYO -> Panasonic
零件编号
产品描述 (功能)
比赛名单
LC89975M Datasheet PDF : 7 Pages
| |||
Control Pin
CONT
Low
High
Mode
(typical example)
PAL/GBI
4.43 NTSC
LC89975M
Chrominance signal delay
(number of CCD stages)
2H (1705) + 0H (2.5)
1H (847) + 0H (2.5)
Luminance signal delay
(number of CCD stages)
1H (849)
1H (843)
Switching levels
Low/High
Symbol
min
typ
max
Unit
Low
High
VL
–0.3
0.0
+0.5
V
VH
2.0
5.0
6.0
V
Note: Since a pull-down resistor of about 70 kΩ is built in the control pin circuit, it will remain fixed at the low level if
left open.
3fsc Pin
This pin outputs the 3·fsc clock signal generated by the PLL 3× circuit.
Electrical Characteristics at VDD = 5.0 V, Ta = 25°C, FCLK = 4.43361875 MHz, VCLK = 500 mVp-p
Parameter
Power-supply current
Switch states
Symbol Test conditions
min
SW1
SW2
SW3
IDD-1
1
IDD-2
a
a
b
27
b
a
b
typ
max
Unit
32
37
mA
No. 5391-3/7
Share Link: 