HD74HC166 查看數據表（PDF） - Hitachi -> Renesas Electronics
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HD74HC166 Datasheet PDF : 10 Pages
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HD74HC166
Parallel-load 8-bit Shift Register
Description
This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register
either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in
parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock
inhibit or Clock. Clear is asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating
one of the clock inputs to act as a clock inhibit.
Features
• High Speed Operation: tpd (Clock to QH) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Clear
L
H
H
H
H
H
Shift/Load
X
X
L
H
H
X
Clock Inhibit Clock
X
X
L
L
L
L
L
H
Serial
X
X
X
H
L
X
Parallel
A ··· H
X
X
a ··· h
X
X
X
Internal Outputs
QA
QB
L
L
QA0
QB0
a
b
H
QAn
L
QAn
QA0
QB0
Output
QH
L
QH0
h
QGn
QGn
QH0
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