ML4826-2 查看數據表（PDF） - Fairchild Semiconductor

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ML4826-2

PFC and Dual Output PWM Controller Combo

Fairchild Semiconductor 

PRODUCT SPECIFICATION

ML4826

ISENSE

x Former

4 x IN4148

T3

200:1

Q14

PN2222

D1

C26

220pF

R16

471Ω

R21

8.63kΩ

C11

1000pF

17 VCC

18 VREF

7 RTCT

R40

47.0kΩ

RAMP2

9

1.5V

AGND

11

1V

R13

2.2kΩ

10 DC ILIMIT

R38

10.0kΩ

U2

VDC

6

PWM CMP

–

+

DC ILIMIT

–

+

Figure 4. Slope Compensation and Current Sense

There are a number of different ways to supply VCC to the

ML4826. The method suggested in Figure 5, is one which

keeps the ML4826 ICC current to a minimum, and allows for

a loosely regulated bootstrap winding. By feeding external

gate drive components from the base of Q1, the constant cur-

rent source does not have to account for variations in the gate

drive current. This helps to keep the maximum ICC of the

ML4826 to a minimum. Also, the current available to charge

the bootstrap capacitor from the bootstrap winding is not

limited by the constant current source. The circuit guarantees

that the maximum operating current is available at all times

and minimizes the worst case power dissipation in the IC.

Other methods such as a simple series resistor are possible,

but can very easily lead to excessive ICC current in the

ML4826. Figures 6 and 7 show other possible methods for

feeding VCC.

Leading/Trailing Modulation

Conventional Pulse Width Modulation (PWM) techniques

employ trailing edge modulation in which the switch will

turn on right after the trailing edge of the system clock. The

error amplifier output voltage is then compared with the

modulating ramp. When the modulating ramp reaches the

level of the error amplifier output voltage, the switch will be

turned OFF. When the switch is ON, the inductor current will

ramp up. The effective duty cycle of the trailing edge modu-

lation is determined during the ON time of the switch. Figure

8 shows a typical trailing edge control scheme.

In the case of leading edge modulation, the switch is turned

OFF right at the leading edge of the system clock. When the

modulating ramp reaches the level of the error amplifier

output voltage, the switch will be turned ON. The effective

duty-cycle of the leading edge modulation is determined

during the OFF time of the switch. Figure 9 shows a leading

edge control scheme.

One of the advantages of this control technique is that it

requires only one system clock. Switch 1 (SW1) turns off

and switch 2 (SW2) turns on at the same instant to minimize

the momentary “no-load” period, thus lowering ripple volt-

age generated by the switching action. With such synchro-

nized switching, the ripple voltage of the first stage is

reduced. Calculation and evaluation have shown that the

120Hz component of the PFC’s output ripple voltage can be

reduced by as much as 30% using this method.

REV. 1.0.4 7/31/01

11

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