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SPT7922 查看數據表(PDF) - Signal Processing Technologies

零件编号
产品描述 (功能)
比赛名单
SPT7922
SPT
Signal Processing Technologies SPT
SPT7922 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
Figure 3 - Analog Equivalent Input Circuit
VCC
VIN
VFT
VEE
The analog input range will scale proportionally with respect
to the reference voltage if a different input range is required.
The maximum scaling factor for device operation is ± 20% of
the recommended reference voltages of VFT and VFB. How-
ever, because the device is laser trimmed to optimize perfor-
mance with ± 2.5 V references, the accuracy of the device
will degrade if operated beyond a ± 2% range.
An example of a recommended reference driver circuit is
shown in figure 2. IC1 is REF-03, the +2.5 V reference with
a tolerance of 0.6% or +/- 0.015 V. The potentiometer R1 is
10 kand supports a minimum adjustable range of up to
150 mV. IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1% with good
TC tracking to maintain a 0.3 LSB matching between VFT and
VFB. If 0.1% matching is not met, then potentiometer R4 can be
used to adjust the VFB voltage to the desired level. R1 and R4
should be adjusted such that VST and VSB are exactly +2.0 V
and -2.0 V respectively.
The following errors are defined:
+FS error = top of ladder offset voltage = (+FS -VST)
-FS error = bottom of ladder offset voltage = (-FS -VSB)
Where the +FS (full scale) input voltage is defined as the
output 1 LSB above the transition of 1—10 and 1—11 and
the -FS input voltage is defined as the output 1 LSB below the
transition of 0—00 and 0—01.
ANALOG INPUT
VIN is the analog input. The full scale input range will be 80%
of the reference voltage or ±2 volts with VFB=-2.5 V and
VFT=+2.5 V.
The drive requirements for the analog inputs are minimal when
compared to conventional Flash converters due to the
SPT7922’s extremely low input capacitance of only 5 pF and
very high input impedance of 300 k. For example, for an input
signal of ± 2 V p-p with an input frequency of 10 MHz, the peak
output current required for the driving circuit is only 628 µA.
CLOCK INPUT
The SPT7922 is driven from a single-ended TTL input (CLK).
The CLK pulse width (tpwH) must be kept between 15 ns and
300 ns to ensure proper operation of the internal track-and-
hold amplifier. (See timing diagram.) When operating the
SPT7922 at sampling rates above 3 MSPS, it is recom-
mended that the clock input duty cycle be kept at 50% to
optimize performance. (See figure 4.) The analog input
signal is latched on the rising edge of the CLK.
The clock input must be driven from fast TTL logic (VIH 4.5 V,
TRISE <6 ns). In the event the clock is driven from a high
current source, use a 100 resistor in series to current limit
to approximately 45 mA.
Figure 4 - SNR vs Clock Duty Cycle
67
65
63
61
59
DCuyctyle=
tpwH
tpwL
57
tpwH tpwL
55
53
51
30
35
40
45
50
55
60
65
70
75
Duty Cycle of Positive Clock Pulse (%)
DIGITAL OUTPUTS
The format of the output data (D0-D11) is straight binary.
(See table II.) The outputs are latched on the rising edge of
CLK with a propagation delay of 14 ns (typ). There is a one
clock cycle latency between CLK and the valid output data.
(See timing diagram.)
Table II - Output Data Information
ANALOG INPUT
>+2.0 V + 1/2 LSB
+2.0 V -1 LSB
0.0 V
-2.0 V +1 LSB
<-2.0 V
OVERRANGE
D12
OUTPUT CODE
D11-DO
1
1111 1111 1111
O
1111 1111 111Ø
O
ØØØØ ØØØØ ØØØØ
O
OOOO OOOO OOOØ
O
OOOO OOOO OOOO
(Ø indicates the flickering bit between logic 0 and 1).
The rise times and fall times of the digital outputs are not
symmetrical. The propagation delay of the rise time is
typically 14 ns and the fall time is typically 6 ns. (See figure
5.) The nonsymmetrical rise and fall times create approxi-
mately 8 ns of invalid data.
SPT
8
SPT7922
3/10/97

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