MAS9142AUA1-T 查看數據表（PDF） - Micro Analog Systems Oy

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MAS9142AUA1-T

Power Amplifier Controller (PAC) and 2.8 V, 50 mA LDO Voltage Regulator

Micro Analog Systems Oy 

BLOCK DIAGRAM

DA9142.002

4 January, 2002

OAMINUS 1

FB

16 OAOUT

DTEMP

2

DRECT

3

PSENSE 4

Diode

bias

+

OA

adder

15 VDD1

14 TXEN

13 VAPC

VSS1

5

RAMP

6

CBYPASS 7

VRCTRL 8

REF

GEN

PIN CONFIGURATION

OAMINUS

DTEMP

DRECT

PSENSE

VSS1

RAMP

CBYPASS

VRCTRL

Power

Down

Control

VOLTAGE

REGULATOR

MAS9142

12 VROUT

11 ENREF

10 VDD2

9 VSS2

OAOUT

VDD1

TXEN

VAPC

VROUT

ENREF

VDD2

VSS2

Top Marking Definitions:

YYWW = Year Week

PIN DESCRIPTION

Pin name

Pin No Type

Function

OAMINUS

1

I

OA Inverting Input (for Optional External Feedback Components)

DTEMP

2

I

Schottky Diode for Temperature Compensation

DRECT

3

I

RF Rectifier Schottky Diode

PSENSE

4

I

Power Measurement Input (from Directional Coupler)

VSS1

5

G

Ground for Power Amplifier Controller

RAMP

6

I

GSM Power Ramping Signal Input

CBYPASS

7

I

Voltage Regulator Reference Voltage Bypass Capacitor

VRCTRL (note 1) 8

I

Voltage Regulator Enable

VSS2

9

G

Ground for Voltage Regulator

VDD2

10

P

Supply for Voltage Regulator

ENREF (note 1) 11

I

Voltage Reference Enable ('warm-up')

VROUT

12

O

Voltage Regulator Output

VAPC

13

O

Automatic Power Control Output Voltage (to PA)

TXEN (note 1)

14

I

Transmit Enable

VDD1

15

P

Supply for Power Amplifier Controller

OAOUT

16

O

OA Output (for Optional External Feedback Components)

NOTE 1:Digital control pads with pull-down resistor, Active-High, CMOS-compatible voltage levels.

G = Ground, I = Input, O = Output, P = Power

2 (11)

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