AD9226(2000) 查看數據表（PDF） - Analog Devices
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AD9226 Datasheet PDF : 28 Pages
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AD9226
DIGITAL SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.)
Parameters
LOGIC INPUTS (Clock, DFS1, Duty Cycle1, and
Output Enable1)
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current (VIN = AVDD)
Low-Level Input Current (VIN = 0 V)
Input Capacitance
Output Enable1
Temp
Full
Full
Full
Full
Full
Full
LOGIC OUTPUTS (With DRVDD = 5 V)
High-Level Output Voltage (IOH = 50 µA)
Full
High-Level Output Voltage (IOH = 0.5 mA)
Full
Low-Level Output Voltage (IOL = 1.6 mA)
Full
Low-Level Output Voltage (IOL = 50 µA)
Full
Output Capacitance
Test Level Min
Typ
IV
2.4
IV
IV
–10
IV
–10
V
5
IV
DRVDD – 0.5
2
IV
4.5
IV
2.4
IV
IV
5
Max
Unit
V
0.8
V
+10
µA
+10
µA
pF
DRVDD + 0.5 V
2
V
V
0.4
V
0.1
V
pF
LOGIC OUTPUTS (With DRVDD = 3 V)
High-Level Output Voltage (IOH = 50 µA)
Full IV
2.95
High-Level Output Voltage (IOH = 0.5 mA)
Full IV
2.80
Low-Level Output Voltage (IOL = 1.6 mA)
Low-Level Output Voltage (IOL = 50 µA)
Full IV
Full IV
NOTES
1LQFP package.
Specifications subject to change without notice.
V
V
0.4
V
0.05
V
SWITCHING SPECIFICATIONS (TMIN to TMAX with AVDD = 5 V, DRVDD = 3 V, CL = 20 pF)
Parameters
Temp
Test Level Min
Typ
Max Conversion Rate
Clock Period1
CLOCK Pulsewidth High2
CLOCK Pulsewidth Low2
Output Delay
Pipeline Delay (Latency)
Output Enable Delay3
Full
VI
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
65
15.38
3
3
3.5
7
15
NOTES
1The clock period may be extended to 10 µs without degradation in specified performance @ 25°C.
2When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle.
3LQFP package.
Specifications subject to change without notice.
Max Unit
MHz
ns
ns
ns
7
ns
Clock Cycles
ns
ANALOG
n
INPUT
n+1 n+2
n+3
n+4
n+8
n+5
n+7
n+6
REV. 0
CLOCK
DATA
n–8
n–7
n–6
n–5
OUT
n–4
n–3
n–2
n–1
n
n+1
Figure 1. Timing Diagram
–3–
TOD = 7.0 MAX
3.5 MIN
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