XRT84V24IV-160 查看數據表（PDF） - Exar Corporation
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XRT84V24IV-160 Datasheet PDF : 6 Pages
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PRELIMINARY
QUAD E1 FRAMER IC XRT84V24
REV. 1.0.1
GENERAL DESCRIPTION
The XRT84V24 Quad E1 Framer IC contains four in-
dependent E1 Framer blocks. Each E1 Framer block
contains its ownTransmit and Receive E1 Framin
function, Transmit HDLC Controller (which encapsu-
lates contentsof Transmit HDLC Buffers into LAPD
Message frames) and Receiver HDLC Controller
(which extracts payload content of “Receive LAPD
Message” frames from the incoming E1 data stream
and writes it into the Receive HDLC Buffer). Each
framer also contains aTransmit and Overhead Input
port, which permits “Data Link” Terminal equipment
direct access to the outbound E1 frames and a Re-
ceive Overhead Output port, which permits “Data
Link” Terminal equipment direct access to the “Data
Link” bits within the inbound E1 frames.
FEATURES
• Four independent, ITU-T G.704 compliant Trans-
ceiver E1 Framers
• Supports Channel Associated Signalin
• Supports Common-Channel and Primary Rate
ISDN Signalin
• Supports FAS, CRC-Multiframe and CAS Multi-
frame framing stuctures
• Contains two 96 byteTransmit HDLC Buffers and
two 96 byte Receive HDLC buffers for each channel
• Contains Microprocessor Interface for popular
types of Microprocessors and supports Pro-
grammed I/O, Burst and DMA modes of Read/Write
access
• Each framer block can encode or decode the E
Frame data into/from the Single-Rail or Dual-Rail
(AMI or HDB3 encoded) formats
• Detects and forces RAI and AIS Alarms
• Detects LOF, COFA and LOS conditions
• Each Framer Contains a 512 bit Elastic Store Buffer
• Uses a Single +3.3V Power Supply
• Available in either a 160 pin PQFP and 208 pin
PQFP package
APPLICATIONS
• SDH terminal or add/drop multiplexers supporting
E1 framing
• E1 multiplexers
• Channel Service Units (CSUs)
• LAN routers with integrated E1 interfaces
• E1 Frame Relay Interface
• ISDN Primary Rate Interfaces
• Test Equipment
FIGURE 1. BLOCK DIAGRAM OF THE XRT84V24
TxPOS_0
TxNEG_0
TxLineClk_0
GPO_6_CS_L_3
GPO_5_CS_L_2
GPO_4_CS_L_1
GPO_3_CS_L_0
GPO_2_SClK_L
GPO_1_SDI
GPO_0_SDO
RxPOS_0
RxNEG_0
RxLineClk_0
Transmit E1
LIU Interface
Transmit E1
Framer
LIU
Controller
Block
HDLC
Controller
Receive E1
LIU Interface
Receive E1
Framer
Framer Block 0
Framer Block 1
Framer Block 2
Framer Block 3
Transmit E1
Overhead Input
Interface
TxOH_0
TxOHClk_0
Transmit E1
Serial Input
Interface
TxLAPD
Buffer
Rx LAPD
Buffer
TxSER_0
TxSERClk_0
Microprosser
Interface Block
PCS_L
PWR_L
PRD_L
PD[7:0]
PA[5:0]
Receive E1
Serial Output
Interface
Receive E1
Overhead Output
Interface
RxSER_0
RxSERClk_0
RxOH_0
RxOHClk_0
1
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