![](/html/Motorola/109236/page4.png)
VDD
16
PULSE
GENERATOR 1
PULSE
GENERATOR 2
5
CLOCK
Q0
2
6 POLARITY Q0
3
4
Q1
10
D0
Q1
9
7
D1
Q2
11
13
D2
14
D3
Q2
12
Q3
1
Q3
15
NOTE: CL connected to output under test.
8 VSS
20* ns
20 ns
CLOCK INPUT
P.G. 1
DATA INPUT
P.G. 2
Q OUTPUT
90%
10%
20 ns
50%
tWH
90%
50%
tsu
th
tPLH
90%
50%
10%
* Input clock rise time is 20 ns except for maximum rise time test.
Figure 2. AC Test Circuit and Timing Diagram
(Clock to Output)
MOTOROLA CMOS LOGIC DATA
MC14042B
159