5962R9582101QQC 查看數據表（PDF） - Intersil

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5962R9582101QQC

Radiation Hardened CMOS High Performance Programmable DMA Controller

Intersil 

Waveforms

HS-82C37ARH

CS

IOW

A0-A3

DB0-DB7

TIWLIWH

TAVIWL

INPUT VALID

TDVIWH

INPUT VALID

TIWHAX

TIWHAX

TIWHDX

FIGURE 1. SLAVE MODE TIMING

NOTE: Host system must allow at least TCLCL as recovery time between successive write accesses.

CS

A0-A3

IOR

TAVIRL

ADDRESS MUST BE VALID

TIRLIRH

TIRLDV

TIRHAX

TIRHDZ

DB0-DB7

DATA OUT VALID

FIGURE 2. SLAVE MODE READ

NOTE: Host system must allow at least TCLCL as recovery time between successive write accesses.

S2

S3

SW

SW

S4

CLK

READ†

TCHRWL

TCHRWL

TCHRH

TCHRWL

TCHWH

WRITE†

READY

EXTENDED

WRITE

TCLRYX

TRYVCL

TCLRYX

TRYVCL

FIGURE 3. READY

†READ refers to both IOR and MEMR outputs. WRITE refers to both IOW and MEMW outputs.

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