HS-82C55ARH(1995) 查看數據表（PDF） - Intersil

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HS-82C55ARH
(Rev.:1995)

Radiation Hardened CMOS Programmable Peripheral Interface

Intersil 

HS-82C55ARH

Operating Modes

MODE 2 (Strobed Bidirectional Bus I/O)

The functional configuration provides a means for communi-

cating with a peripheral device or structure on a single 8-bit

bus for both transmitting and receiving data (bidirectional

bus I/O). “Handshaking” signals are provided to maintain

proper bus flow discipline similar to MODE 1. Interrupt gen-

eration and enable/disable functions are also available.

Mode 2 Basic Functional Definitions:

• Used in Group A only.

• One 8-bit, bidirectional bus port (Port A) and a 5-bit control

port (Port C).

• Both inputs and outputs are latched.

• The 5-bit control port (Port C) is used for control and

status for the 8-bit, bidirectional bus port (Port A).

Bidirectional Bus I/O Control Signal Definition

INTR (Interrupt Request)

A high on this output can be used to interrupt the CPU for

both input or output operations. INTR will be set either by the

rising edge of ACK (INTE1 = 1) or the rising edge of STB

(INTE2 = 1). INTR will be reset by the falling edge of WR (if

previously set by the rising edge or ACK), the falling edge of

RD (if previously set by the rising edge of STB), or the falling

edge of WR when immediately following a low RD pulse or

the falling edge of RD when immediately following a low WR

pulse (if previously set by the rising edges of both ACK and

STB).

CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0

10

1/0 1/0 1/0

PC2 - PC0

1 = INPUT

0 = OUTPUT

PORT B

1 = INPUT

0 = OUTPUT

GROUP B MODE

0 = MODE 0

1 = MODE 1

FIGURE 20. MODE CONTROL WORD

PC3

PA7- PA0

PC7

INTE PC6

1

INTR A

8

OBF A

ACK A

INTE

2

PC7

STB A

WR

PC6

IBF A

RD

3

PC2- PC0

I/O

FIGURE 21. MODE 2 (BIDIRECTIONAL)

Output Operations

OBF (Output Buffer Full)

The OBF output will go “low” to indicate that the CPU has

written data out to Port A.

ACK (Acknowledge)

A “low” on this input enables the tri-state output buffer of Port

A to send out the data. Otherwise, the output buffer will be in

the high impedance state.

INTE 1 (The INTE Flip-Flop Associated with OBF)

Controlled by Bit Set/Reset of PC6.

Input Operations

STB (Strobe Input)

A “low” on this input loads data into the input latch.

IBF (Input Buffer Full F/F)

A “high” on this output indicates that data has been loaded

into the input latch.

INTE 2 (The INTE Flip-Flop Associated with IBF)

Controlled by Bit Set/Reset of PC4.

WR

OBF

TWHOL

INTR

ACK

STB

DATA FROM CPU

TO HS-82C55ARH

TKHOL

TSLSH

TKLKH

IBF

PERIPHERAL

BUS

TSLIH

TKLPV

TPVSH

TSHPX

RD

DATA FROM PERI-

PHERAL TO

HS-82C55ARH

DATA FROM

HS-82C55ARH

TO PERIPHERAL

TKHPX

TRHIL

DATA FROM

HS-82C55ARH

TO CPU

NOTE: Any sequence where WR occurs before ACK and STB occurs

before RD is permissible.

FIGURE 22. MODE 2 (BIDIRECTIONAL)

Spec Number 518060

988

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