HS-82C55ARH 查看數據表（PDF） - Intersil

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HS-82C55ARH

Radiation Hardened CMOS Programmable Peripheral Interface

Intersil 

HS-82C55ARH

TABLE 3.

A1 A0 RD WR CS

DISABLE FUNCTION

X

X

1

1

0 Data Bus - 3-State

CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0

GROUP B

PORT C (LOWER)

1 = INPUT

0 = OUTPUT

PORT B

1 = INPUT

0 = OUTPUT

MODE SELECTION

0 = MODE 0

1 = MODE 1

GROUP A

PORT C (UPPER)

1 = INPUT

0 = OUTPUT

PORT A

1 = INPUT

0 = OUTPUT

MODE SELECTION

00 = MODE 0

01 = MODE 1

1X = MODE 2

MODE SET FLAG

1 = ACTIVE

FIGURE 11. MODE SET CONTROL WORD FORMAT

Mode Selection

There are three basic modes of operation that can be

selected by the system software:

Mode 0 - Basic Input/Output

Mode 1 - Strobed Input/Output

Mode 2 - Bidirectional Bus

When the RESET input goes “high”, all ports will be set to

the input mode with all 24 port lines held at the logic “one”

level by internal bus hold devices. After reset, the

HS-82C55ARH can remain in the input mode with no

additional initialization required. This eliminates the need for

pull-up or pull-down resistors in all CMOS designs. During

the execution of the system program, any of the other modes

may be selected using a single output instruction. This

allows a single HS-82C55ARH to service a variety of

peripheral devices with a simple software maintenance

routine.

The modes for Port A and Port B can be separately defined

while Port C is divided into two portions as required by the

Port A and Port B definitions. All of the output registers,

including the status register, will be reset whenever the

mode is changed. Modes may be combined so that their

functional definition can be “tailored” to almost any I/O

structure. For instance: Group B can be programmed in

Mode 0 to monitor simple switch closings or display

computational results, Group A could be programmed in

Mode 1 to monitor a keyboard or tape recorder on an

interrupt-driven basis.

The mode definitions and possible mode combinations may

seem confusing at first but after a cursory review of the

complete device operation a simple, logical I/O approach will

surface. The design of the HS-82C55ARH has taken into

account things such as efficient PC board layout, control

signal definition vs PC layout and complete functional

flexibility to support almost any peripheral device with no

external logic. Such design represents the maximum use of

the available pins.

CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0

XX X

DON’T

CARE

BIT SET/RESET

1 = SET

0 = RESET

BIT SELECT

01234567

0 1 0 1 0 1 0 1 B0

0 0 1 1 0 0 1 1 B1

0 0 0 0 1 1 1 1 B2

BIT SET/RESET FLAG

0 = ACTIVE

FIGURE 12. BIT SET/RESET CONTROL WORD FORMAT

Single Bit/Set/Reset Feature

Any of the eight bits of Port C can be Set or Reset using a

single OUTput instruction. See Figure 12. This feature

reduces software requirements in control-based

applications.

Interrupt Control Functions

When the HS-82C55ARH is programmed to operate in Mode

1 or Mode 2, control signals are provided that can be used

as interrupt request inputs to the CPU. The interrupt request

signals, generated from Port C, can be inhibited or enable by

setting or resetting the associated INTE flip-flop, using the

Bit Set/Reset function of Port C.

This function allows the programmer to enable or disable a

CPU interrupt by a specific I/O device without affecting any

other device in the interrupt structure.

INTE Flip-Flop Definition:

(BIT-SET) - INTE is SET - Interrupt enable.

(BIT-RESET) - INTE is RESET - Interrupt disable.

NOTE: All mask flip-flops are automatically reset during mode

selection and device Reset.

8

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