CD4070 查看數據表（PDF） - Intersil
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CD4070 Datasheet PDF : 8 Pages
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Schematics
VDD
CD4070BMS, CD4077BMS
p
B*
2 (5, 9, 12)
n
n
p
VSS
VDD
VDD
p
p
p
A*
1 (6, 8, 13)
n
n
VDD
VSS
VSS
p
J
3 (4, 10, 11)
n
TRUTH TABLE CD4070BMS
1 OF 4 GATES
A
B
J
0
0
0
1
0
1
0
1
1
1
1
0
1 = High Level
0 = Low Level
J = A⊕B
* ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070BMS (1 OF 4 IDENTICAL GATES)
VDD
VDD
p
p
B*
2 (5, 9, 12)
n
n
n
p
VSS
VDD
p
A*
1 (6, 8, 13)
n
n
VDD
VSS
VSS
p
J
3 (4, 10, 11)
n
TRUTH TABLE CD4077BMS
1 OF 4 GATES
A
B
J
0
0
1
1
0
0
0
1
0
1
1
1
1 = High Level
0 = Low Level
J = A⊕B
* ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077BMS (1 OF 4 IDENTICAL GATES)
7-460
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