5962R9582001QJC 查看數據表（PDF） - Intersil
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5962R9582001QJC Datasheet PDF : 18 Pages
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HS-82C85RH
Internal logic requires that the SLO/FST pin be held low for
at least 195 oscillator or EFI clock pulses before the SLOW
mode command is recognized. This requirement eliminates
unwanted FAST-to-SLOW mode frequency changes which
could be caused by glitches or noise spikes.
To guarantee FAST mode recognition, the SLO/FST pin
must be held high for at least 3 OSC or EFI pulses. The
HS-82C85RH will begin FAST mode operation on the next
PCLK edge after FAST command recognition. Proper CLK
and CLK50 phase relationships are maintained and
minimum pulse width specifications are met.
FAST-to-SLOW or SLOW-to-FAST mode changes will occur
on the next rising or falling edge of PCLK. It is important to
remember that the transition time for operating frequency
changes, which are dependent upon PCLK, will vary with the
HS-82C85RH oscillator or EFI frequency.
Slow/Fast Mode Control
The HS-82C55ARH programmable peripheral interface can
be used to provide slow/fast mode control by connecting one
of the port pins directly to the SLO/FST pin (see Figure 21).
With the port pin configured as an output, software control of
the SLO/FST pin is provided by simply writing a logical one
(FAST mode) or logical zero (SLOW Mode) to the
corresponding port. PORT C is well-suited for this function
due to its bit set and reset capabilities.
CLK
HS-82C85RH
CLOCK
CONTROLLER
GENERATOR
SLO/FST
HS-82C55RH
PERIPHERAL
INTERFACE
PC0
CLK
HS-80C86RH
μPROCESSOR
D0 - 8
FIGURE 21. SLOW/FAST MODE CONTROL USING
HS-82C55RH PERIPHERAL INTERFACE
Alternate Operating Modes
Using alternate modes of operation (slow, stop-clock, stop-
oscillator) will reduce the average system operating power
dissipation in a static CMOS system (see Table 2). This does
not mean that system speed or throughput must be reduced.
When used appropriately, the slow, stop-clock, stop-
oscillator modes can make your design more power-efficient
while maintaining maximum system performance.
Oscillator
The oscillator circuit of the HS-82C85RH is designed
primarily for use with an external parallel resonant,
fundamental mode crystal from which the basic operating
frequency is derived. The crystal frequency must be three
times the required CPU clock. X1 and X2 are the two crystal
input connections. The output of the oscillator is buffered
and available at the OSC output (pin 18) for generation of
other system timing signals.
TABLE 2. TYPICAL SYSTEM POWER SUPPLY CURRENT
FOR STATIC CMOS OPERATING MODES
FAST
STOP- STOP-
SLOW CLOCK OSC
CPU Frequency
5MHz 20kHz
DC
DC
XTAL Frequency 15MHz 15MHz 15MHz
DC
IDD
HS-80C86RH
50mA 2.5mA 250μA 250μA
HS-82C85RH
24.7mA 16.9mA 14.1mA 24.4μA
HS-82C08RH
1.0mA 10.0μA 1.0μA
1.0μA
82C82
1.7mA 6.5mA
1.0μA
1.0μA
HS-82C54RH
943.0μA 915.0μA 1.0μA
1.0μA
HS-82C55ARH
3.2μA
1.2μA
1.0μA
1.0μA
74HCXX + Other 2.9mA 110.0μA 90.0μA 90.0μA
HS-65262RH
4.0mA 50.0μA 10.0μA 10.0μA
HS-6617RH
6.3mA 52.5μA 12.0μA 12.0μA
NOTE: All measurements taken at room temperature, VDD = +5.0V.
Power supply current levels will be dependent upon system
configuration and frequency of operation.
For the most stable operation of the oscillator (OSC) output
circuit, two capacitors (C1 = C2) are recommended.
Capacitors C1 and C2 are chosen such that their combined
capacitance matches the load capacitance as specified by
the crystal manufacturer. This insures operation within the
frequency tolerance specified by the crystal manufacturer.
The crystal/capacitor configuration and the formula used to
determine the capacitor values are shown in Figure 22.
Crystal Specifications are shown in Table 3. For additional
information on crystal operation, see Intersil publication Tech
Brief 47.
X1
C1
CRYSTAL
2.4MHz - 15MHz
X2
C2
CT=
-C-----1----•-----C----2---
C1 + C2
(Including stray capacitance)
FIGURE 22. CRYSTAL CONNECTION
14
FN3044.3
April 20, 2007
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