5962F9568901V9A 查看數據表（PDF） - Intersil

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5962F9568901V9A

Radiation Hardened Quad Differential Line Receiver

Intersil 

Pinouts

HS1-26C32RH

(16 LD SBDIP)

MIL-STD-1835: CDIP2-T16

TOP VIEW

AIN 1

AIN 2

AOUT 3

ENABLE 4

COUT 5

CIN 6

CIN 7

GND 8

16 VDD

15 BIN

14 BIN

13 BOUT

12 ENABLE

11 DOUT

10 DIN

9 DIN

HS-26C32RH

AIN

AIN

AOUT

ENABLE

COUT

CIN

CIN

GND

HS9-26C32RH

(16 LD FLATPACK)

MIL-STD-1835: CDFP4-F16

TOP VIEW

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

VDD

BIN

BIN

BOUT

ENABLE

DOUT

DIN

DIN

Propagation Delay Timing Diagram

-VIN

+VIN = 0V

VOH

VOL

INPUT

tPLH

VS = 50%

0V

tPHL

OUTPUT

+2.5V

-2.5V

Propagation Delay Load Circuit

DUT

CL

TEST

POINT

RL

CL = 50pF

RL = 1000Ω

Three-State Low Timing Diagram

VIH

VSS

VOZ

VOL

VS

INPUT

tPZL

VT

tPLZ

OUTPUT

VW

Three-State High Timing Diagrams

VIH

VSS

VOH

VOZ

VS

INPUT

tPZH

VT

tPHZ

OUTPUT

VW

2

FN3402.4

August 1, 2008

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