IS61C12816 查看數據表（PDF） - Integrated Silicon Solution

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IS61C12816

128K x 16 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61C12816

ISSI ®

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

Symbol Parameter

-12

-15

-20

Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time

12 —

15 —

20 —

ns

tSCE CE to Write End

9—

10 —

12 —

ns

tAW Address Setup Time

to Write End

9—

10 —

12 —

ns

tHA Address Hold from Write End 0 —

0—

0—

ns

tSA Address Setup Time

0—

0—

0—

ns

tPWB LB, UB Valid to End of Write 9 —

10 —

12 —

ns

tPWE WE Pulse Width

9—

10 —

12 —

ns

tSD Data Setup to Write End

6—

7—

9—

ns

tHD Data Hold from Write End

0—

0—

0—

ns

tHZWE(2) WE LOW to High-Z Output

—

6

—7

—9

ns

tLZWE(2) WE HIGH to Low-Z Output

3—

3—

3—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input

pulse levels of 0 to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not

100% tested.

3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All

signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write.

The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that

terminates the write.

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

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