IDT71V509S50Y 查看數據表（PDF） - Integrated Device Technology
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IDT71V509S50Y
Integrated Device Technology
IDT71V509S50Y Datasheet PDF : 9 Pages
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IDT71V509
128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBT™ AND FLOW-THROUGH OUTPUT
PIN CONFIGURATION
COMMERCIAL TEMPERATURE RANGE
A0
1
A1
2
A2
3
VSS
4
I/O7
5
I/O6
6
VDD
7
I/O5
8
I/O4
9
OE
10
VDD
11
VSS
12
VSS
13
I/O3
14
I/O2
15
VDD
16
I/O1
17
I/O0
18
VSS
19
NC (2)
20
A3
21
A4
22
44
43
42
41
40
39
38
37
36
35
SO44-1
34
33
32
31
30
29
28
27
26
25
24
23
NC (4)
A16
A15
A14
A13
A12
A11
WE
VDD(5)
CLK
VSS
VDD
NC (1)
CS
CEN
A10
A9
A8
A7
A6
A5
NC(3)
Notes:
1. Pin 32: Future control input
2. Pin 20: Future I/O8
3. Pin 23: Future A17
4. Pin 44: Future A18
5. Pin 36 does not need to be connected directly to VDD, as long as it is ≥ VIH.
TOP VIEW
3618 drw 02
PIN DEFINITIONS(1)
Symbol
Pin Function
I/O
A0-A16
Address Inputs
I
CLK
Clock
I
CEN
Clock Enable
I
CS
Chip Select
I
WE
Write Enable
I
OE
Output Enable
I
I/O0-I/O7 Data Input/Output I/O
VDD
VSS
Power Supply
N/A
Ground
N/A
Active
N/A
N/A
LOW
LOW
LOW
LOW
N/A
N/A
N/A
Description
Synchronous Address inputs. The address is registered on every rising edge
of CLK if CEN and CS are both low.
The clock input. Except for OE, all input and output timing references for the
device are with respect to the rising edge of CLK.
Synchronous clock enable input. When CEN is sampled high, the other
synchronous inputs are ignored, and outputs remain unchanged. When CEN
is sampled low, the IDT71V509 operates normally.
Synchronous chip select input. When CS is sampled low, the device operates
normally. When CS is sampled high, no read or write operation is initiated,
and the I/O bus is tri-stated the next cycle. CS is ignored if CEN is high at
the same rising edge of CLK.
Synchronous write enable. If WE is sampled low, a write is initiated at the
address that is registered at that time. If WE is sampled high, a read is initiated
at the address that is registered at that time. WE is ignored when either CEN
or CS is sampled high.
Asynchronous output enable. When OE is high, the I/O bus goes high
impedance. OE must be low to read data from the IDT71V509.
Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.
3.3V power supply pins.
Ground pins.
11.3
2
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