IDT71V509S66Y 查看數據表（PDF） - Integrated Device Technology

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IDT71V509S66Y

128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBT™ AND FLOW-THROUGH OUTPUT

Integrated Device Technology 

IDT71V509

128K X 8 3.3V SYNCHRONOUS SRAM WITH ZBT™ AND FLOW-THROUGH OUTPUT

AC ELECTRICAL CHARACTERISTICS

(VDD = 3.3V ±5%, TA = 0 to 70°C)

Symbol

Parameter

Clock Parameters

fMAX

tCYC

tCH

Clock Frequency

Clock Cycle Time

Clock High Pulse Width

tCL

Clock Low Pulse Width

Output Parameters

tCD

tCDC

tCLZ(1)

tCHZ(1)

tOE

tOLZ(1)

tOHZ(1)

Clock High to Valid Data

Clock High to Data Change

Clock High to Output Active

Clock High to Data High-Z

Output Enable Access Time

Output Enable Low to Data Active

Output Enable High to Data High-Z

Set Up Times

tSE

Clock Enable Setup Time

tSA

Address Setup Time

tSD

Data In Setup Time

tSW

Write Enable Setup Time

tSC

Chip Select Setup Time

Hold Times

tHE

Clock Enable Hold Time

tHA

Address Hold Time

tHD

Data In Hold Time

tHW

Write Enable Hold Time

tHC

Chip Select Hold Time

NOTES:

1. Transition is measured ±200mV from steady-state.

COMMERCIAL TEMPERATURE RANGE

IDT71V509S66 IDT71V509S50

Min. Max. Min. Max. Unit

—

66

—

50 MHz

15

—

20

—

ns

5

—

6

—

ns

5

—

6

—

ns

—

9

—

10

ns

2

—

2

—

ns

2

—

2

—

ns

2

5

2

6

ns

—

6

—

7

ns

0

—

0

—

ns

—

5

—

6

ns

2

—

2.5

—

ns

2

—

2.5

—

ns

2

—

2.5

—

ns

2

—

2.5

—

ns

2

—

2.5

—

ns

1

—

1

—

ns

1

—

1

—

ns

1

—

1

—

ns

1

—

1

—

ns

1

—

1

—

ns

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

0 to 3V

2ns

1.5V

1.5V

See Figures 1 and 2

AC TEST LOADS

I/O

Z0 = 50Ω

+1.5V

50Ω

30pF

Figure 1. AC Test Load

3618 drw 04

+3.3V

317Ω

I/O

351Ω

5pF*

3618 drw 05

Figure 2. AC Test Load

(for tOHZ, tCHZ, tOLZ, and tDC1)

* Including scope and jig

11.3

7

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